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Based on the lessons learned, we discuss the vulnerabilities and potentials of logic locking uncovered by SnapShot. The results indicate that the security foundation of common logic locking schemes is built on questionable assumptions. Moreover, SnapShot outperforms the existing technique on all evaluated benchmarks. The evaluation results show that SnapShot achieves an average key prediction accuracy of 82.60% for the selected attack scenario, with a significant performance increase of 10.49 percentage points compared to the state of the art. We perform an extensive evaluation of SnapShot for two realistic attack scenarios, comprising both reference combinational and sequential benchmark circuits as well as silicon-proven RISC-V core modules. The attack flow offers a generic and customizable framework for attacking locking schemes using machine learning techniques. The second approach utilizes genetic algorithms to evolve more complex convolutional neural network architectures specialized for the given task. The first approach is based on a simple feedforward fully connected neural network.
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Hereby, the attack uses a simpler yet more flexible learning model compared to existing work. Therefore, in this article we present SnapShot, a novel attack on logic locking that is the first of its kind to utilize artificial neural networks to directly predict a key bit value from a locked synthesized gate-level netlist without using a golden reference. As in most research branches, deep learning is being introduced in the domain of logic locking as well. However, in recent years, the security of locking schemes has been thoroughly challenged by the introduction of various deobfuscation attacks. Logic locking is a prominent technique to protect the integrity of hardware designs throughout the integrated circuit design and fabrication flow. We hope that our research can inspire RISC-V researchers and developers.
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Based on our survey, we predict the future research and development directions of RISC-V security. Our survey covers hardware and physical access security, hardware-assisted security units, ISA security extensions, memory protection, cryptographic primitives, and side-channel attack protection. Then, we investigate the security research of RISC-V around the theme of hardware and architecture security. Specifically, we first briefly introduce the background and development status of RISC-V, and compare the RISC-V mechanisms with the most relevant Arm mechanisms, highlighting their similarities and differences. This paper summarizes the representative security mechanisms of RISC-V hardware and architecture. In order to fill this research gap, this paper presents an in-depth survey on RISC-V security technologies. The latest technology and future development direction of RICS-V security research are still unclear. Many RISC-V security research projects are underway, but the academic community has not yet conducted a comprehensive survey of RISC-V security solutions. In order to deal with foreseeable security threats, the RISC-V community is studying security solutions aimed at achieving a root of trust (RoT) and ensuring that sensitive information on RISC-V devices is not tampered with or leaked. Data security and user privacy protection are common challenges faced by all IoT devices. Many important operating systems and major tool chains have supported RISC-V. Many companies have already owned or are designing RISC-V processors.
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In recent years, the free and open RISC-V ISA standard has attracted the attention of industry and academia and is becoming the mainstream. For decades, these processors were mainly based on the Arm instruction set architecture (ISA). Embedded processors are the processing engines of smart IoT devices. The Internet of Things (IoT) is an ongoing technological revolution.